1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device in which the test functions of a built-in test circuit are activated in response to a test mode setting signal, which is applied to an external connection terminal and is higher than a voltage applied thereto in a normal operation mode.
Recently, semiconductor integrated circuit devices have been designed to have advanced functions and an increased integration density. It takes an extremely long time to test such semiconductor integrated circuit devices in order to detect defects introduced during the production process. Under the above circumstances, a semiconductor integrated circuit device with a built-in test circuit has been developed in which the test functions of a built-in test circuit are activated in response to a test mode setting signal, which is applied to an external connection terminal and is higher than a voltage applied thereto in a normal operation mode.
2. Description of the Prior Art
FIG. 1 shows an essential feature of a semiconductor integrated circuit device 1 as described above. The semiconductor integrated circuit device 1 includes an external connection terminal 2 to which a normal signal is applied in a normal operation mode. For example, the normal signal has a high potential level of 5 [V] and a low potential level of 0 [V]. In a test mode, a test mode setting signal higher than 5 [V] is applied to the external connection terminal 2.
The device 1 includes an input first-stage circuit 3, which receives the signal applied to the external connection terminal 2. The device 1 includes a test mode setting signal detecting circuit 4, which detects the test mode setting signal applied to the external connection terminal 2. The device 1 includes a test function activating signal generating circuit 5, which generates a test function activating signal when the test mode setting signal is detected by the test mode setting signal detecting circuit 4.
The test mode setting signal detecting circuit 4 and the test function activating signal generating circuit 5 are configured as shown in FIG. 2. The detecting circuit 4 includes n-channel metal oxide semiconductor (hereinafter simply referred to as nMOS) transistors 6.sub.1, 6.sub.2, 6.sub.3, . . . , 6.sub.n-1 and 6.sub.n (n is an integer) and an nMOS transistor 7. The gate of the nMOS transistor 7 is connected to a VCC power supply line, which supplies a power supply voltage of, for example, 5 [V]. The generating circuit 5 includes an inverter 9.
The nMOS transistors 6.sub.1 -6.sub.n are connected in series so that the gates thereof are connected to the drains thereof and the drains and sources are located on the external terminal 2 side and the ground side, respectively. The threshold voltages V.sub.TH of the nMOS transistors 6.sub.1 -6.sub.n are selected so that V.sub.TH .times.n&gt;5 [V]. The drain of the nMOS transistor 7 is connected to the source of the nMOS transistor 6.sub.n, and the source thereof is grounded. In the normal operation mode, the nMOS transistor 7 is continuously ON. The ON resistance of the nMOS transistor 7 is set equal to, for example, 1 megaohm to a few megaohms.
The inverter 9 has an input terminal
connected to a node 10 at which the source of the nMOS transistor 6.sub.n is connected to the drain of the nMOS transistor 7, and an output terminal via which the test function activating signal is output.
In the test mode setting signal detecting circuit 4 and the test function activating signal generating circuit 5, when the normal signal having the 5 [V] high level and the 0 V low level is applied to the external connection terminal 2, the nMOS transistors 6.sub.1 -6.sub.n are not turned ON because the threshold voltages V.sub.TH of these transistors are higher than 5 [V]. Hence, the node 10 is at the ground level (0 [V]), and the output of the inverter 9 is high (at the high level).
When a voltage higher than V.sub.TH .times.n is applied to the external connection terminal 2 as the test mode setting signal, the nMOS transistors 6.sub.1 -6.sub.n are turned ON, and the level of the node 10 becomes high, and the output signal of the inverter 9 is switched to the low level. This low-level signal is applied to a test control signal generating circuit (not shown) as the test function activating signal.
In the above-mentioned manner, it becomes possible to detect the test mode setting signal and generate the test function activating signal with a simple structure for the circuits 4 and 5.
FIG. 3 is a graph of input leak characteristics of the test mode setting signal detecting circuit 4. In the graph of FIG. 3, a solid line 11 relates to a case where the threshold voltage of the test mode setting signal detecting circuit 4 is comparatively low, and a solid line 12 relates to a case where the threshold voltage of the circuit 4 is comparatively high. When the input leak characteristic indicated by the solid line 11 is selected, an input leak occurs due to the input signal applied to the external connection terminal 4 in the normal operation. When the input leak characteristic indicated by the solid line 12 is selected, the input leak does not occur due to the input signal applied to the terminal 4, but the input first-stage circuit 3 may be destroyed due to the test mode setting signal being required to be higher than the high level in the normal operation.
With the above in mind, the threshold voltage of the test mode setting signal detecting circuit 4 is selected so as to be high enough to prevent the test mode setting signal from destroying the input first-stage circuit 3 and prevent occurrence of the input leak.
However, the threshold voltages V.sub.TH of the nMOS transistors 6.sub.1 -6.sub.n are not equal to each other due to factors introduced during the production process. When the nMOS transistors 6.sub.1 -6.sub.n have deviations from the designed threshold voltage, the deviation of the threshold voltage of the test mode setting signal detecting circuit 4 is equal to n times the sum of the deviations of the nMOS transistors 6.sub.1 -6.sub.n, and hence has a great deviation.
Even in the case that the threshold voltage of the test mode setting signal detecting circuit 4 is selected so as to be high enough to prevent the test mode setting signal from destroying the input first-stage circuit 3 and prevent occurrence of the input leak, the input leak will occur if the threshold voltage of the detecting circuit 4 greatly deviates from the designed value toward the low-potential side because of factors introduced during the production process. Devices having the input leak are handled as defective devices.
Further, the test mode setting signal can be changed stepwise only because the threshold voltage of the test mode setting signal detecting circuit 4 can be controlled stepwise only.